Semiconductor data storage devices, such as semiconductor memories and registers, typically access or output multiple-bit stored data in response to an applied signal or signals.
A race condition is a problem that can be caused in such a devices when there is a difference between a speed at which an address signal (ADD) input to the device is transmitted and the speed at which an address valid (ADV) signal and the data is transmitted. This difference in speed arises from design constraints of the integrated circuit (IC) or chip, and the different paths over which the signals propagate. Typically, a time margin equal to or greater than the worst case difference is added to the access time to ensure that all switching of signals has ended before an output signal is latched or data read.
The general state of the art with respect to solving the race condition problem may be understood with reference to the circuit 100 illustrated in FIG. 1. Referring to FIG. 1, ADD and ADV signals are applied to an input latch 102 and logic device 104 as shown. The address signal (ADD) is latched on a rising edge of the ADV signal. Data from one or more data storage elements 106 is provided to an output latch 108 though a multiplexer (MUX 110), and is typically updated from a different clock domain and synchronized with respect to ADV on the output of the logic elements or device 104. New ADD and ADV signals are then applied to get next data.
One problem with the above conventional approach is a “race condition” arises in which synchronization delays and a pulse width of the ADV signal can cause differences between ADD and ADV signals resulting in the wrong data 106 being driven out of the output latch device 108. A conventional approach to avoiding or minimizing this race condition is to take a worst case delay for synchronization of the ADD and ADV signals as a reference delay and generating a clock or a control signal based on this reference delay to gate the circuits to be selected, thereby providing a hold condition constraint for the output latch.
Typically, these timing constraints are calculated and applied late in the design cycle during a physical design stage, affecting other unrelated physical design activities, and requiring numerous iterations.
Accordingly, there is a need for a circuit and method of using the same that substantially eliminates race conditions and the uncertainty associated therewith by design. It is further desirable that the circuit and method eliminate costs and delays incurred through repeated calculation and application of timing constraints late in the design cycle.